The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. These advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.
Such scaling-down requires minimal tolerance for impurities and contaminants present during the processing and manufacturing of ICs. The presence of even small amounts of impurities and contaminants negatively affects the fabrication processes and resulting fabricated devices. Current efforts to reduce contamination arising from external sources (e.g., human sources) and internal sources (e.g., within the process chambers) include improving the quality of clean rooms, utilizing automated equipment to minimize exposure, and introducing various cleaning methods within process chambers. However, particularly when dealing with contaminated process chambers, conventional cleaning methods still produce undesirable results. For example, when considering individual wafer lots, current cleaning methods produce a first wafer effect and poor wafer to wafer critical dimension difference within a wafer lot. This requires each wafer lot to include a few dummy wafers to undergo processing so that all the actual wafers processed reflect uniform critical dimensions and properties, resulting in increased costs and increased production times. Further, current cleaning methods require longer than desirable cleaning times between wafer lots, resulting in increased mean time between clean of wafer lots and increased damage to the exposed process chambers.
Accordingly, what is needed is a method for cleaning process chambers that addresses the above stated issues.